发明名称 EXCLUSIVE LOGICAL SUM CIRCUIT
摘要 PURPOSE:To form a complementary exclusive logical sum circuit with a reduced number of the component element by containing three units of the first conductive MISFFT plus three units of the second conductive MISFFT and securing the mutual control with the input signal of the other side. CONSTITUTION:P-type MISFETQ3 and Q4 which are controlled by the signals of input terminal B and A of the other side are provided between input terminal A and B and output terminal X, and then n-type MISFETQ1 is installed between terminal X and reference potential terminal V2 to be controlled by the output signal of terminal X'. Then n-type MISFETQ5 and Q6 are provided between terminal A and B and terminal X', and P-type MISFETQ2 is installed between terminal X' and power source V1. When the levels of power source V1 and V2 are set to 1 and 0 respectively, FETQ5 and Q6 are turned on with Q4 and Q4 turned off respecitvely. At the same time, Q1 is turned on with Q2 turned off, and output X and X' become to the levels of 0 and 1 respectively. Thus, the output of exclusive OR is obtained at terminal X, and the output of exclusive NOR is obtained at terminal X' respectively. The action of this circuit is shown in the truth value table.
申请公布号 JPS5456350(A) 申请公布日期 1979.05.07
申请号 JP19770122372 申请日期 1977.10.14
申请人 HITACHI LTD 发明人 KOBAYASHI ISAMU;TAKANASHI AKIRA
分类号 H03K19/0944;H03K19/0948;H03K19/21 主分类号 H03K19/0944
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