| 摘要 |
PURPOSE:To interrupt memory cycle operation by resetting forcibly the control circuit of a memory module unselected. CONSTITUTION:Memory address signal 1 is decoded by signal 3 with logical value ''1''. Memory access request signal 2 sets R-S flip-flop 8 and output signal 5 of flip- flop 8 is supplied to memory control part 12. Memory access signal 2 after being delayed by delay circuit 9 and signal 3 are AND-ed by AND circuit 10 and when memory module 15 is unselected, signal 6 has logical valur ''1'' and memory control part 12 and flip-flop 8 are both reset. In addition, signal 6 resets flip-flop 8 through OR circuit 11. |
