发明名称 FAULT TOLERANT LEAST RECENTLY USED ALGORITHM LOGIC
摘要 <p>FAULT TOLERANT LEAST RECENTLY USED ALGORITHM LOGIC Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 valid binary bit combinations that reflect the sequence of use of the four units. The provision of 6 binary bits in the LRU code are capable of assuming 64 different permutations, therefore 40 combinations of binary bits are considered invalid when utilizing the LRU code. The present invention utilizes certain of the invalid binary bit combinations to identify units that have been removed from further use because of a fault condition, and which code continues to identify the sequence of use of those units which have not been eliminated from further use. The code chosen to identify a faulty unit and the sequence of use of the remaining units is fault tolerant in that additional errors in the coding mechanism can be tolerated, and ignored, while maintaining the ability to identify faulty units and sequence of use of the remaining units.</p>
申请公布号 CA1053804(A) 申请公布日期 1979.05.01
申请号 CA19760247255 申请日期 1976.03.02
申请人 COOMBES, DANIEL J.;MESSINA, BENEDICTO U. 发明人 COOMBES, DANIEL J.;MESSINA, BENEDICTO U.
分类号 G06F11/20;G06F11/00;G06F12/12;(IPC1-7):06F7/00 主分类号 G06F11/20
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