| 摘要 |
PURPOSE:To remarkably simplify the circuit constitution, by selecting either of the reception digital signal or the delayed digital signal, through the detection of the varying point detection signal and the phase of clock. CONSTITUTION:The circuit consists of the delay circuit DL, differentiation circuits DF1 and DF2, AND gates A1 and A2, FF FF1, FF2 and selection circuit SEL. The reception digital signal is delayed with the circuit DL, the varying of the delayed digital signal and the reception digital signal is detected with the circuits DF1 and DF2, the phase of the carrying point detection signal and the clock cl is detected with the gates A1 and A2, thus, either of the reception digital signal or the delayed digital signal is selected with the circuit SEL, and read in is made by using the clock cl through FF2. Further, the front time margin in reading in FF2, the output pulse width of DF1 and DF2 assures and the rear time margin is assured by the pulse width of the clock cl. |
