| 摘要 |
PURPOSE:To remarkably increase the processing efficiency for the data processing unit, by extending the period of the output clock as required. CONSTITUTION:When the signal RDER representing the presence of the read error correctable is taken place, signal RESTB is occurred, the state of FF16, 17 is fixed, the high level signal of signals QBC, PFCK is extended, NAND condition is taken for the signals QBC, PFCK with the NANK circuit 20, and the low level signal of the clock XFCK is extended. Since one readout cycle is from the leading of the clock XFCK to the next leading, if the signal RDER is inputted, the readout cycle can be extended. (Figure shows the case with the extension of 1/4 readout cycle period) |
