| 摘要 |
A circuit for converting an input analog signal into a digital representation and a remainder signal is disclosed. The digital representation is generated by a coder that counts an integral number of clock cycles during an interval in which the magnitude of the input analog signal is compared with the magnitude of a ramp signal. The remainder signal is generated by duration-to-amplitude conversion of a pulse whose duration is the fractional remainder of the final uncounted clock cycle. |
