DIFFERENTIAL PULSE CODED SYSTEM USING SHIFT REGISTER COMPANDING

摘要

DIFFERENTIAL PULSE CODED SYSTEM USING SHIFT REGISTER COMPANDING A digital accumulator employing a reversible shift register converts a 1-bit differential pulse code to a logarithmically companded, or n:m, pulse code. The accumulator is coupled through a digital-to-analog converter to a subtraction circuit which also receives an analog signal to be represented in the differential pulse code. Output from the subtractor is integrated and thresholded to produce the differential pulse code. A decoder using the same type of accumulator is also shown.