| 摘要 |
PURPOSE:To eliminate the delay of access operation by leading out a terminal from the timing chain circuit of a memory unit and by connecting a gate circuit to it. CONSTITUTION:Signals are applied to starting signal register 10, write register 20, refresh register 21, normal address register 30, and write data register 40 as shown in the figure and, for example, at the time of a read/write cycle, memory address signal MAD with a certain delay from a normal address rise is applied from address switching circuit 2 to meory array 1. Then, timing chain circuit 4 outputs signals Tcl and Tc2, which are delayed from output EN of register 10 by Td1 and Td2, to AND gate 5 and OR gate 6. Consequently, a tip enable signal at the time of reading and writing/refreshing is generated independently, and the access time at the time of reading can be shortened. |
