发明名称 TIMEEDIVISION SWITCHING SYSTEM
摘要 PURPOSE:To simplify the connection control between circuit-signal concentrating- expansion parts and a circuit signal bread-down-makeup device by controlling connections among those devices by one switching memory, by providing a switching gate circuit among them. CONSTITUTION:This system is provided with a plural number of circuit signal concentrator-expanders A0, A1, and A2 which concentrate and expand signals from a plural number of circuit groups G0, G1 and G2 through respective circuits, and switching gate circuit SWG, which is arranged among devices A0, A1 and A2, controlling transfer signals. Further, circuit-signal breakdown-makeup device SSR, which changes signals from circuits or signals from the switching unit to respective circuits into the information states of corresponding destinations, is connected to circuit SWG. Next, switching memory units SWM and CPU are connected between device SSR and circuit SWG; device SWM is stored with information for circuit connection setting, and the CPU makes the administration and control of device SWM, so that the connections between devices A0, A1 and A2, and circuit SWG will be controlled in a time-division mode.
申请公布号 JPS5449006(A) 申请公布日期 1979.04.18
申请号 JP19770115084 申请日期 1977.09.27
申请人 OKI ELECTRIC IND CO LTD;KOKUSAI DENSHIN DENWA CO LTD 发明人 HARA TAKEHIRO;MATSUBARA HIDEYUKI;UCHIYAMA HARUHIKO;INUZUKA KENZOU;NISHIMURA TAKESHI
分类号 H04Q11/04;(IPC1-7):04Q11/04 主分类号 H04Q11/04
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