| 摘要 |
A method of manufacturing a silicon gate MIS device using ion implantation and controlled ion scattering to provide concurrent formation and automatic alignment of the gate structure and adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents-typically oxide and silicon-are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to the predetermined gate size beneath the overhanging mask. The photoresist mask is then used during ion implantation of the source and drain to establish the lateral surface boundaries within which ions are implanted. These lateral surface boundaries are selected so that as the ions are driven into the substrate to the desired junction depth of the source and drain by lateral scattering, the source and drain are aligned with the silicon gate electrode.
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