Fail-safe timing circuit

摘要

This disclosure relates to a fail-safe timing circuit having a regulator which produces a regulated d.c. voltage when a switch is closed. A signal generator powered by the regulated d.c. voltage for producing square-wave signals. A two-stage amplifier for amplifying the square-wave signals which are fed to a dual rectifier network which produces a positive d.c. voltage and a regulated negative fail-safe d.c. voltage. A pulse generator powered by the positive d.c. voltage for producing signal pulses having an unequal duty cycle. A charging circuit connected to the regulated negative d.c. voltage, and a trigger circuit for periodically sampling the potential charge on the charging circuit. An amplifier for amplifying periodic pulses which are produced during the sampling of the potential charge. A level detector for producing a.c. oscillations when the level of the periodic pulses exceeds a predetermined value, an amplifier for amplifying the a.c. oscillations, and a rectifier for rectifying the amplified a.c. oscillations to produce a d.c. output voltage for energizing a relay upon expiration of a given time interval after the switch is closed.