| 摘要 |
PURPOSE:To enable high speed processing, even if the memory slow in response speed is used, by controlling the amount of transfer depending on the amount of program processing. CONSTITUTION:The timing generator 13 can be constituted, for example, with the serial parallel out IC elements, and the period T is determined with the necessity of process control which is the object of protection control. In the steady state condition of process, since the output of the output decoder 12 is ''0'' and the signal of the control end is also ''0'', the Q output of FF11 is ''0'' and the Q output is ''1''. Therefore, the output of the AND gate 14 and that of the AND gate 16 are respectively the same as the output waveform of (a) and (c). Accordingly, the control for the input control circuit and the memory transfer control circuit if performed in the timing of (a) and (c), and the write-in to RAM 3 for the process condition amount is made at the period of to t1 and the program transfer from EPROM 10 to RAM 3 is made at the period of t2-t3. |
