| 摘要 |
PURPOSE:To realize the detection which regards it as an error even when the bits of a transmitted code are all ''1'' or ''0'', by detecting an error judging from whether the remainder through division exists or not by presetting the redundant bit of the shift register of a divider circuit to which information bits and the 2nd redundant bit are transmitted. CONSTITUTION:The divider circuit consists of shift registers D0, D1...Dm-2, adders AD0, AD1...ADm-2 interposed between respective stages of registers D0...Dm-2 corresponding to coefficients of the generating polynomial, and the feedback input circuit. Now, the 1st redundant bit, which is indivisible by generating polynomial G(X), is selected and preset to registers D0...Dm-2 of the divider circuit, and the 2nd redundant bit, i.e. the remainder is added which is obtained by dividing the code of information bits and the 1st redundant bit by polynomial G(X). At the reception dide, on the other hand, the redundant bit of the shift registers of the divider circuit supplied with information bits and the 2nd redundant bit is preset and it is detected whether or not the remainder through this division exists, thereby detecting an error even when the bits of the transmission code are all ''1'' or ''0''. |
