| 摘要 |
PURPOSE:To enable to write in and read out in high speed, by using low speed memories, through the split processing of memory write-in and readout. CONSTITUTION:When the write-in mode in designated with the control circuit 8, the input signal fed to the terminal 13 is alternately and respectively memorized in FF6, 7 for data memory with the clock signals 11 and 12 frequency-divided 5 into 1/2. That is the time memorized in FF6, 7 is twice the period of the clock signal 10. Further, the location of either of memories 1, 2 memorizing the content of FF6, 7 is determined with the address counters 3 and 4, and since the counters 3 and 4 are operated in synchronizing with FF6, 7, the input signal is stored split in the memories 1, 2 in the speed of clock signal. That is, in this case, the clock signal can be taken twice the processing ability of memory. Further, similarly, in the case of readout, the output of memories 1, 2 can be gated and alternately read out with the output selection circuit 9 by the output signal 11 of FF5. |
