发明名称 MEMORY ERASING METHOD
摘要 <p>PURPOSE:Several memory integrated-circuits are grouped into one or more, one common erasing power supply is connected to each group via a switching method, and an erasing voltage is applied while giving a fixed time delay to each group, thereby erasing several memories in a short time with a small-capacity power supply. CONSTITUTION:Applying an erasing voltage avalanche-injects memory erasing charge into memory cells, thereby erasing memory contents. In this method mentioned above, the memory of the integrated-circuit is divided into memory groups M1, M2...Mn which power supply PS is able to supply an erasing voltage. Then, power supply PS is connected via relay contacts C1, C2...Cn which correspond to memory groups M1, M2...Mn respectively. Those relay contacts C1, C2...Cn are closed by connection control circuit CK being delayed respectively by a fixed time, thereby applying sequentially an erasing voltage to memory groups M1, M2...Mn with a fixed time difference.</p>
申请公布号 JPS5443634(A) 申请公布日期 1979.04.06
申请号 JP19770110270 申请日期 1977.09.13
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 MIZUSAWA TAKESHI
分类号 G11C17/00;G11C11/34;G11C16/02;G11C16/16 主分类号 G11C17/00
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