| 摘要 |
A correction circuit for arithmetic operations with non-hexadecimal operands in hexadecimal arithmetic units incorporates a full hexadecimal adder for each four-bit word of the operands, a carry storage register coupled to a carry output of the full adder and to its own output, and a coupling circuit for selectively coupling to an operand input of the full adder an operand or a correction factor or the output of the carry storage register. The adder has a second operand input and an output which is connected to a memory for storing a sum output of the adder. The coupling circuits are controllable so that a carry produced by arithmetic operations involving two operands is stored in the carry storage register. In a subsequent arithmetic operation involving the sum of the first arithmetic opration and a correction factor, the carry storage register is connected to its own output and to the carry output of the adder. In a third arithmetic operation the output of the carry storage register is connected to the operand input which corresponds to the correction factor while the correction factor is being added or subtracted to the previously produced sum. |
