Detection circuit for short circuited thyristor - employs logic gates responsive to voltage and trigger signals

摘要

The circuit is typically applicable to HV equipment employing cells in series. A logic gate (G) is supplied with signals representing positive and negative thyristor cell voltage (Up, Un), and trigger impulse (F). A fourth input (A) is derived from the gate output via a time delay (M). The combined output of the gate (G) is arranged to give a logic function representing the inverse of the inputs. Typically the gate is a NOR gate, and the time delaya monostable flip-flop. Recognition of a fault can be used to trigger the remaining series devices thus preventing breakdown due to overvoltage.