| 发明名称 |
ERROR CORRECTION PROCESS SYSTEM |
| 摘要 |
PURPOSE:To enable a judgement whether bit wi is incorrect or not among k-units of the bit when the multiple errors are caused and thus to enable the correction for the adjacent error, by adopting the magnified H matrix to satisfy the specified condition. |
| 申请公布号 |
JPS5442953(A) |
申请公布日期 |
1979.04.05 |
| 申请号 |
JP19770102914 |
申请日期 |
1977.08.26 |
| 申请人 |
FUJITSU LTD |
发明人 |
MATSUZAWA KAZUMITSU;TOUMA YOSHIHIRO |
| 分类号 |
G06F11/10;G06F12/16;G11C29/00;H03M13/00 |
主分类号 |
G06F11/10 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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