发明名称 FAIL-SAFE SOLID STATE LOGIC
摘要 A fail-safe solid state logic system based on the use of an AC input signal of one type, and a DC input which causes a logical gate to convert the AC input signal to a totally different AC output signal; that is, to one adapted to be received by a vital driver or the like, which is tuned to accept only that different AC output signal and no other. Accordingly, the failures which are most likely to occur, namely, shorts from input to output or failure to toggle, result in the AC signal frequency not being changed and as a consequence, the system fails safe.
申请公布号 ZA7801409(B) 申请公布日期 1979.03.28
申请号 ZA19780001409 申请日期 1978.03.10
申请人 GENERAL SIGNAL CORP 发明人 SIBLEY H
分类号 B61L1/20;H02H3/05;H03K19/007 主分类号 B61L1/20
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