| 摘要 |
For increasing the availability of a modular computer, a control unit and switches are provided, the latter being connected in between the control storages and the remaining identical hardware of the processor. In the case of a hardware error of one processor, its control storage is switched for a specific period of time to the same hardware of another processor which interrupts its own tasks, assuming the tasks of the defective processor for the time during which the control storage of the defective processor remains switched off. Subsequently, the former or non-defective processor resumes its own tasks. The task cycles assigned to one processor or the other can be specified to be identical or as a function of the respective processing requirements. |
