| 摘要 |
1. A system for transmitting individual images which are either stationary or which move during recording, comprising a television camera (1) ; a first analogue-digital converter (2) ; a digital transmitter image repetition store (3) for the transmission of images which are not at least virtually stationary ; a transmitter buffer store (4) ; either a digital transmission channel or an analogue transmission channel (5) which is limited by a first digital-analogue converter and a second analogue-digital converter ; a digital receiver image repetition store (7) ; a receiver buffer store (6) ; a second digital-analogue converter (8) ; and a television receiver (9), characterized in that the transmitter image repetition store (7) and the receiver image repetition store consist of CCD (charge coupled device) image repetition stores, that the transmitter buffer store (4) consists of a first register (13) whose inputs are used as inputs of the transmitter buffer store (4), a first store (14) whose inputs are connected to the outputs of the first register (13), a second register (15) whose inputs are connected to the outputs of the first store (14) and whose outputs serve as outputs of the transmitter buffer store (4), a first multiple change-over switch (16) whose outputs are connected to address inputs of the first store (14), a first multiple change-over switch control (17) whose output is connected to a control input of the first multiple change-over switch (16), a first counter (18) whose resetting input serves as an image pulse input and whose data outputs are connected to first inputs of the first multiple change-over switch (16), a second counter (19) whose outputs are connected to second inputs of the first multiple change-over switch (16), a third register (20) whose inputs are connected to data outputs of the first counter (18), a comparator (21) whose first inputs are connected to the inputs of the third register (20) and whose second inputs are connected to the outputs of the third register (20) a third counter (22) whose over-flow output is connected to a clock pulse input of the third register (20), a first phase shift device (23) whose input is connected to the output of a second clock pulse generator (24) and whose output is connected to a read clock pulse input of the first store (14), to a clock pulse input of the second register (15), to a clock pulse input of the second counter (19), and to a backwards clock pulse input of the third counter (22), a switch (25) whose setting input is connected to an output of the comparator (21) and whose output is connected to a write clock pulse input of the first store (14) and to a forwards clock pulse input of the third counter (22) whose overflow output is connected to a resetting input of the switch (25), and a first clock pulse generator (26) whose output is connected to the clock pulse input of the first register (13), to the input of the first multiple change-over switch control (17), to a clock pulse of the first counter (18), to a clock pulse input of the first phase shift device (23), and to an input of the switch (25), and that moreover the receiver buffer store (6) consists of a fourth register (27) whose input are used as inputs of the receiver buffer store (6), a second store (28) whose inputs are connected to outputs of the fourth register (27), a fifth register (29) whose inputs are connected to outputs of the second store (28) and whose outputs serve as outputs of the receiver buffer store (6), a second multiple change-over switch (30) whose outputs are connected to address inputs of the second store (28), a second multiple change-over switch control (31) whose output is connected to the control input of the second multiple change-over switch (30), a fourth counter (32) whose resetting input serves as an image pulse input and whose data outputs are connected to first inputs of the second multiple change-over switch (30), a fifth counter (33) whose data outputs are connected to second inputs of the second multiple change-over switch (30), a sixth register (34) whose data inputs are connected to the data outputs of the fourth counter (32), a second comparator (35) whose first inputs are connected to clata inputs of the sixth register (34) and whose second inputs are connected to the data outputs of the sixth register (34), a sixth counter (36) whose overflow output is connected to the clock pulse input of the sixth register (34), a second phase shift device (37) whose input is connected to an output of a fourth clock pulse generator (24') and whose output is connected to a write clock pulse input of the second store (28), to a clock pulse input of the fourth register (27), to the input of the fifth counter (33), and to a backwards clock pulse input of the sixth counter (36), a second switch (38) whose setting input is connected to an output of the second comparator (35), whose output is connected to the read clock pulse input of the second store (28), to an image store output (39), to a clock pulse input of the fifth register (29), and to the forwards clock pulse input of the sixth counter (36) whose overflow output is connected to the resetting input of the switch (38), and a third clock pulse generator (26') whose output is connected to an input of the second multiple change-over switch control (31), to a clock pulse input of the fourth counter (32), to a clock pulse input of the second phase shift device (37), and to the input of the second switch (38) (Figures 3 and 5). |
