发明名称 Phase locked loop frequency synthesizer using digital modulo arithmetic
摘要 A reference source of digital pulses of a first frequency f1 is coupled to the input of a frequency synthesizer which is capable of providing a second frequency f2 output signal. The second frequency is related to the first frequency by a predetermined, rational fraction (e.g., as f2 = (M/N)f1). The synthesizer includes a phase control unit comprising an adder by way of which a first number N is added each sample period to a remainder, the sum output of the adder being operated upon modulo a second number M, e.g., by dividing by M and discarding a resultant quotient to obtain a remainder. The remainder, having a value between zero and M-1, is compared to a prefixed signal, illustratively the largest integer in M/2. If the remainder is less than the prefixed signal, a first logic state control signal is provided to a control system; else a second logic state signal is so provided. The alternation between the first and second logic states is such that M pulses of the second frequency occur for every N pulses of the first frequency. Thereby, the second frequency is synthesized responsive to the first.
申请公布号 US4145667(A) 申请公布日期 1979.03.20
申请号 US19770832831 申请日期 1977.09.13
申请人 BELL TELEPHONE LABORATORIES, INCORPORATED 发明人 MESSERSCHMITT, DAVID G.
分类号 H03L7/18;(IPC1-7):H03B3/04 主分类号 H03L7/18
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