| 摘要 |
A read-only-memory is provided on a semiconductor chip having a reduced number of power supply lines. The memory has a plurality of storage cells arranged in an array. Vertical lines define columns of the memory. Every other vertical line is coupled to a first node. The first node is controllably coupled to a first voltage potential to controllably precharge the first node. The vertical lines not connected to the first node are connected to an output node. P channel field effect transistors are used to couple the vertical lines to the first node and to the output node. A plurality of N-channel field effect transistors controllably couple the vertical lines to a second voltage potential. A vertical line on one side of the column of memory cells is used to provide a precharge voltage to the cell while a vertical line on the other side of the column of memory cells is used to conduct stored information from the cell to the output node. The vertical lines are shared by adjacent columns of memory cells thereby reducing the number of power supply lines.
|
