| 摘要 |
An asynchronous validity checking system and method is disclosed for monitoring a plurality of clock signals carried on separate electrical conductors to assure continuing transitions of each clock signal. A master clock is utilized to produce a plurality of phase-related clock signals on the separate electrical conductors, and the transitions of the clock signals are sensed on each electrical conductor adjacent to the distribution point to a controlled unit to assure that all clock signals are continuously operational. The validity checking system includes a locking synchronizer having a plurality of flip-flops each of which receives a different one of the clock signals and a timing signal from a timing oscillator that is independent of, and asynchronous with respect to, the clock signals from the master oscillator with the clock signals being locked into the flip-flops on the rising leading edges of the pulses of the timing signal. A sequence and presence checking unit receives the output signals from the flip-flops and produces reset pulses which are coupled to digital counters incremented by the falling trailing edges of counter clock pulses that are frequency related to the timing signal pulses coupled to the locking synchronizer. As long as transitions of the clock signals are sensed on each of the electrical conductors to reset the counters within a predetermined period of time, no fault indication is produced. If a transition is not sensed, however, the counters are not reset within the predetermined period of time and a fault indication is produced that is indicative of a defect in a clock signal. Upon sensing of the failure of a transition of a clock signal, a fault indication is produced which may be utilized to automatically effectively stop the clock, selectively switch power off, or switch the master clock from a controlled unit, such as a magnetic recording device, to prevent damage and/or information loss.
|
