摘要 |
<p>The system has an operation defining unit (7) having a control circuit (48), a writing circuit (33) and an operation memory circuit (47). An input of the operation memory circuit is connected to a first output of the control circuit and also to depart (42), final, (43) microcycle (44), cycle (45) and sync. pulses (46) registers. All the aforementioned registers have their first inputs connected to the operation memory circuit (47). Their second inputs are connected to corresponding second outputs of the control circuit and their third outputs are connected to corresponding third outputs of the control circuit.</p> |