| 发明名称 |
CLOCK RATE CONTROL SYSTEM |
| 摘要 |
<p>PURPOSE:To increase the overall process velocity for the bus-type information transfer processor, by changing the duration of the synchronous clock in accordance with the device when the low-speed or high-speed device receives an access.</p> |
| 申请公布号 |
JPS5428535(A) |
申请公布日期 |
1979.03.03 |
| 申请号 |
JP19770093767 |
申请日期 |
1977.08.05 |
| 申请人 |
FUJITSU LTD |
发明人 |
TAKECHI HIROAKI;YAMAZAKI MASASHI;ISOBE HITOSHI |
| 分类号 |
G06F13/42;G06F1/08;G06F1/12;G06F5/06 |
主分类号 |
G06F13/42 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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