A=D conversion error detection - involves signal storage during system cycle, with new value subtracted from old, and result integrated and compared with threshold

摘要

The error appears during analogue-digital conversion. Linear test ramps with certain rate of rise or fall are produced and an analogue-to-digital converted value is stored during a system cycle and the new value is subtracted from the stored value. The result is converted into Gray code, and the code is interrogated with programmed priority. The subtraction result is integrated over an adjustable time base, and the integrated result compared with a freely programmable threshold. A single bit error signal is delivered.