发明名称 |
METOD FOR ATT TESTA CELLERNA I EN HALVLEDARMINNESMATRIES |
摘要 |
Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test. |
申请公布号 |
SE406829(B) |
申请公布日期 |
1979.02.26 |
申请号 |
SE19750006873 |
申请日期 |
1975.06.16 |
申请人 |
* INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
W M * CHU;G * SONODA |
分类号 |
G11C11/413;G06F11/22;G11C11/412;G11C29/00;G11C29/04;G11C29/14;G11C29/50;G11C29/56;(IPC1-7):11C29/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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