发明名称 PEAK VALUE DETECTION CIRCUIT
摘要 PURPOSE:To establish the highly accurate peak value detection circuit, by constituting the circuit with a semiconductor switch operated with the input control clock signal, peak value hold capacitor, and comparison circuit between the peak hold value and the analog input signal.
申请公布号 JPS5425660(A) 申请公布日期 1979.02.26
申请号 JP19770091145 申请日期 1977.07.29
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 ARAKI TAKESHI
分类号 H03K5/1532;H03K5/00 主分类号 H03K5/1532
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