发明名称 CIRCUIT FOR FUNCTIONING/TESTING OF IC FOR WATCH
摘要 PURPOSE:To enable a terminal to set 3 conditions of a watch by a simple mechanism, by controlling opening and closing of a gate and resetting of a counter in accordance with 3-value signal including floating level. CONSTITUTION:When a reset/test terminal 100 is opened to set condition of floating, outputs TQ1 of an inverter 40 and a D type FF 41 and outputs Q2 of an exlusive OR gate 42 and a D type FF 43, etc., to which this outputs Q1 and Q1 passing through inverters 45 and 46 are added, are logically treated by a logical circuit 44, so that outputs ACC and RESET all become logically zero (0). Similarly, by variation of logical values of signals ACC and RESET put out from the circuit 44 in accordance with logic 1 or 0 of a signal added to the terminal 100, opening and resetting of clocked inverters 35 and 34, which form a gate, and resetting of a static frequency dividing circuit 36 are controlled. By doing so, 3 conditions of a step motor including the mormal operation, the resetting and the testing acceleration by frequency dividing output of high frequency are all done by a terminal, and therefore, a circuit for the both functioning and testing of IC for watch is obtained by a simple mechanism.
申请公布号 JPS57125376(A) 申请公布日期 1982.08.04
申请号 JP19810011078 申请日期 1981.01.28
申请人 TOKYO SHIBAURA DENKI KK 发明人 YAGI TAIRA;ODA HIROSHI
分类号 G01R31/28;G01R31/3185;G04C3/00;G04D7/00;G04G5/00;G04G99/00 主分类号 G01R31/28
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