发明名称 Voltage detection circuit composed of at least two MOS transistors
摘要 A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage VDD via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage VDD with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.
申请公布号 US4140930(A) 申请公布日期 1979.02.20
申请号 US19770820320 申请日期 1977.07.29
申请人 SHARP KABUSHIKI KAISHA 发明人 TANAKA, SHINICHI
分类号 G01R19/165;H03K17/30;(IPC1-7):H03K17/20;H03K17/22;H03K17/60 主分类号 G01R19/165
代理机构 代理人
主权项
地址