摘要 |
A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage VDD via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage VDD with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.
|