发明名称 BUS LINE CHEKCING DEVICE
摘要 PURPOSE:To ensure an error detection in a bit correspondence both for the device control bus and the date bus, by including the set signal to be given to the output bus line register and the reading signal which is used to put the output bus line register onto the input bus line into the matrix circuit.
申请公布号 JPS5422137(A) 申请公布日期 1979.02.19
申请号 JP19770086082 申请日期 1977.07.20
申请人 HITACHI ELECTRONICS 发明人 MAEDA ICHIROU;NAKANO KOUJI;OOTA YOSHIHITO
分类号 G06F11/00;G06F3/00;G06F13/00 主分类号 G06F11/00
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