| 摘要 |
A digital signal bypass circuit including a two terminal clock input for supplying a clock input signal with a predetermined first frequency. A divide-by-two squaring circuit is also provided which is input for synchronously translating the clock input signal into an output signal having a frequency one-half of the predetermined first frequency. A bypass circuit is provided which is connected to the clock input and responsive to the clock input signal applied thereto, the bypass circuit being operative to disable the divide-by-two squaring circuit so that the output signal has a frequency equal to the predetermined first frequency.
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