发明名称 TEST PATTERN PREPARING SYSTEM
摘要 PURPOSE:To generate a test pattern signal not to cause the competition of a bus control at the time of generating the test pattern signal of a logical circuit including a bus by providing a bus extracting means, a bus control means and a test pattern preparing means. CONSTITUTION:In the test pattern signal generation of a logical circuit including a bus, a bus extracting means 4 extracts the bus after a first test pattern preparation executed by paying attention to a certain trouble while the input value of a control gate is not determined, and outputs the bus control information to a bus control means 5. The means 5 determines the input value of the control gate so as to make only one bus control effective in accordance with the bus control information. A test pattern preparing means 2, when the control gate input value of the bus is not determined, assigns the defined value to one of the control gate input values of the bus, assigns a high impedance value to others, executes the backward pursuit, and prepares a partial test pattern 7 which is a third test pattern. As needed, by the output of a second test pattern 9, the test pattern signal not to cause the competition of the bus control can be prepared.
申请公布号 JPH02126332(A) 申请公布日期 1990.05.15
申请号 JP19880279761 申请日期 1988.11.04
申请人 NEC CORP 发明人 HARADA EIJI
分类号 G06F11/22;G06F17/50 主分类号 G06F11/22
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