发明名称 Phase lock loop
摘要 A phase lock circuit has a voltage tuned oscillator (VTO) which is tuned by a tuning circuit. The tuning circuit supplies tune-up and tune-down (in frequency) signals to phase lock the VTO with respect to a reference signal. The tuning circuit supplies the tune-up and tune-down signals based on the results of samples of the VTO output from a variable modulus counter (VMC) with respect to a reference signal. The reference signal and VMC are reset to a time reference by a reset generator during coarse tuning or phase locking.
申请公布号 US4138650(A) 申请公布日期 1979.02.06
申请号 US19770779609 申请日期 1977.03.21
申请人 ANDERSON, SCOTT K. 发明人 ANDERSON, SCOTT K.
分类号 H03L7/191;H03L7/199;H04L27/06;(IPC1-7):H03B3/04 主分类号 H03L7/191
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