发明名称 PROGRAMMABLE LOGIC CIRCUIT
摘要 PURPOSE:To efficiently package a sequential circuit by providing an NMOS transistor and a programmable switch at NOR output on each NOR plane. CONSTITUTION:The NMOS transistors T1, T2 whose one terminals are grounded are connected to the output of each (2L) input NOR gate on MX(2L) input NOR planes and that of each (2M) input NOR on NX(2M) input NOR planes. The gates of the transistors T1, T2 are grounded or connected to the output of neighboring NORs with a programmable switch. Also, the transistors T1, T2 and the programmable switch to control the connection of the gates are to constitute a local feedback path. Thereby, it is possible to efficiently package the sequential circuit such as a flip-flop, etc.
申请公布号 JPH03159316(A) 申请公布日期 1991.07.09
申请号 JP19890298519 申请日期 1989.11.16
申请人 NEC CORP 发明人 SAITO SHOICHI
分类号 G06F7/00;H03K19/177 主分类号 G06F7/00
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