SERVOCIRCUITO DI CONTROLLO, DI TIPO DIGITALE.

摘要

The duty cycle of a pulse width modulated signal for controlling a drive motor is determined by the content or numbers stored in a counter and representing phase and/or speed errors. The counter is driven by a clock signal which has a number of cycles during each cycle of the pulse width modulated control signal which is exactly equal to the capacity of the counter. The pulse width modulated signal is initiated by a timing pulse and is terminated by the return to zero of the most significant digit of the counter. The time at which the most significant digit of the counter returns to zero in each cycle is determined by a number initially contained in the counter. The content of the counter is periodically determined according to detected speed and phase errors to update the duty cycle of the pulse width modulated control signal.