| 摘要 |
A clock cycle is provided by a delay device, the output of which is coupled via an inverter to the input thereof, which inverter is combined in a gate structure so as to enable such clock cycle and derivative clock pulses coupled to be generated as a signal passes through the delay device. The gate structure is coupled to receive a so-called stall signal inhibiting the clock system from generating an output. The stall signal so inhibits such clock system only after the present clock cycle is completed. Further, the gate structure is coupled so that a stall signal received and then cleared before the end of the clock cycle will have no effect on the system. The system also responds to a removal or clearing of a stall signal by immediately beginning another clock cycle after the relatively insignificant delay introduced by the gate structure. |
