Synchronous generating circuit devices with two phase-locked loops and feedback around both

摘要

A circuit device for generating a synchronous signal in synchronism with a steady wave component of an input signal and including a first phase-locked loop using the input signal as a reference signal, a second phase-locked loop using an output signal of a voltage controlled oscillator (VCO) of the first phase-locked loop as a reference signal, and a feedback circuit for feeding back and adding an output signal of a VCO of the second phase-locked loop to the input signal. The synchronous signal is stably obtained at the output of the VCO of the second phase-locked loop, even if the level of the steady wave component is relatively low. The level of the fed back signal may be controlled in response to the level of the steady wave component whereby the oscillation of the circuit device may be prevented.