Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching

摘要

An input buffer for utilization in a programmable logic device (PLD). The input buffer includes an inverter consisting of a PMOS pull up transistor one half the size of a corresponding NMOS pull down transistor to enable TTL compatibility. To drive a high capacitance load, instead of utilizing further buffering which introduces gate delays, a cascode transistor is used to control an additional pull up output driver connected to the output of the inverter. The cascode functions to turn on the additional pull up output driver to supplement the PMOS pull up transistor during a low to high transition of the output. The input buffer further includes a switching transistor coupled between a VDD power supply and the PMOS pull up transistor to cut power to the PMOS pull up transistor when the inverter has a low output. With no utilization of power during a low output, the input buffer provides a zero power TTL input enabling the input buffer to be utilized on circuitry in battery powered devices.