发明名称 Data hold circuit
摘要 A data hold circuit storing a logic state of a predetermined node of a logic circuit immediately before power supply to the logic circuit is interrupted, and restoring the stored logic state to the predetermined node immediately after the power supply is restarted. The data hold circuit includes a memory circuit storing the logic state of the node, a switch circuit connected between the memory circuit and the node, and a control circuit controlling the on/off operation of the switch circuit. The control circuit turns on the switch circuit for a predetermined time period when the power supply is changed from on to off, or from off to on. The memory circuit is continuously supplied with power from a power supply other than that for the logic circuit. While the power supply to the logic circuit is in a steady state either in the power on state or power off state, the switch circuit is kept off, thereby preventing effect of the memory circuit on the logic circuit.
申请公布号 US5473571(A) 申请公布日期 1995.12.05
申请号 US19940315247 申请日期 1994.09.29
申请人 NIPPON TELEGRAPH AND TELEPHONE CORPORATION 发明人 SHIGEMATSU, SATOSHI;MUTOH, SHIN'ICHIRO;MATSUYA, YASUYUKI
分类号 G11C14/00;(IPC1-7):G11C13/00 主分类号 G11C14/00
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