Programmable sequential logic system for telecommunication systems - is designed to increase system capacity and manage peripherals sending programme interruption requests

摘要

The system has memory (EM) and interruption management (GIT) extension circuits which are connected to the input bus (BE), to the output bus (BS) and the addressor (BY) of the central unit (UC). The system has a group of memories (MA, MO, MT, MP) addressed by the output bus (BS) of the logic circuit. The memories contain for each processing programme the access conditions for the segment of memory (M). The memories also contain an interruption priority level for each processing programme. The system has also a priority level detection circuit for interruption requests, (DI,T, EP, CP, PC) and safeguard registers (RAC, SRAC, SC) for information necessary for the restarting of an interrupted programme. The group of memories (MO, MT, MA, MP) permit the storage of context. These memories have common addressing provided by a register (RAC) loaded from an output bus (BS) of the central unit (UC).