| 摘要 |
A mixed-modulo address generation unit has several inputs, preferably three. The unit can effectively add together a subset of these inputs in a reduced modulus, and simultaneously add this partial sum to a full-width input using a full modulus, the full modulus being greater than the reduced modulus. Reduced-width address components, such as 16-bit components with a 32-bit adder, are applied to the subset of inputs. The mixed modulo address generation unit sign-extends to 32-bits one input that includes a sign bit, the input being in the subset of inputs. Each input in the subset of inputs is applied to a carry-generate unit which signals if the partial sum is equal to or exceeds the reduced modulus. Under normal conditions, the full-modulus sum from the adder is output as a linear address. However, if the carry-generate unit signals a carry-out, and the sign bit indicates a positive number, then the full-modulus sum is recirculated to one of the adder's inputs and a correction term, equal to the two's complement of the reduced modulus, is added to produce the linear address. If the carry generate unit does not signal a carry-out, but the sign bit indicates a negative number, then the full-modulus sum is recirculated to one of the adder's inputs and a correction term, equal to the reduced modulus, is added to produce the linear address.
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