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发明名称
LOGIC CIRCUIT
摘要
PURPOSE:To establish the logic circuit without increasing the number of transistors and lowering in the output voltage due to base bias effect, by providing P or N channel type MOS FET taking clock pulse as the gate input signal.
申请公布号
JPS54968(A)
申请公布日期
1979.01.06
申请号
JP19770066877
申请日期
1977.06.06
申请人
MITSUBISHI ELECTRIC CORP
发明人
TOMIZAWA TAKASHI
分类号
H03K19/096
主分类号
H03K19/096
代理机构
代理人
主权项
地址
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