| 摘要 |
PURPOSE:To reduce a machine cycle and to improve the computing ability by using a multiplier having an SD display function including the redundancy contained in an internal logic to shorten the computing time for repetitive multiplication at execution of the multiplication, the division and the extraction of the square root. CONSTITUTION:An adder/subtractor 2 is used as an arithmetic element together with a multiplier 3 having an SD display function including the redundancy contained in an internal logic, and a ROM 5 which is used for the multiplication type division and the multiplication type extraction of the square root. At the same time, the registers 6 - 15 are added to two data input parts of the adder/ subtractor 2, two data input parts of the multiplier 3, and a data input part of the ROM 5 respectively. In such a constitution, plural arithmetic operations are carried out with use of a single computing element. Thus it is possible to obtain an arithmetic processor having a small hardware quantity, i.e., a small scale and the multiple functions and to attain the computing operations at a high speed with use of the multiplier 3 applying the SD display function. |
