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经营范围
发明名称
ERROR DETECTION SYSTEM
摘要
PURPOSE:To realize a high-reliability memory unit, by detecting an addressing error by a provided address-check information forming circuit.
申请公布号
JPS53148243(A)
申请公布日期
1978.12.23
申请号
JP19770062947
申请日期
1977.05.30
申请人
FUJITSU LTD
发明人
NAGABORI TETSUO;ISAKA TETSUO
分类号
G06F12/16;G11C29/00
主分类号
G06F12/16
代理机构
代理人
主权项
地址
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