发明名称 Method of forming high density flash memories with high capacitive-couping ratio and high speed operation
摘要 The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanocal polishing the layer. A rugged silicon layer is subsequently deposited over the gate and the polished polysilicon. Then, the floating gate is defined. A dielectric is formed at the top of the rugged silicon. A conductive layer is formed on the dielectric layer as a control gate.
申请公布号 US6008090(A) 申请公布日期 1999.12.28
申请号 US19990261027 申请日期 1999.03.02
申请人 WU, SHYE-LIN 发明人 WU, SHYE-LIN
分类号 H01L21/28;H01L21/336;H01L29/51;(IPC1-7):H01L21/824 主分类号 H01L21/28
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