| 摘要 |
1536853 Multiple access storage systems PLESSEY CO Ltd 8 April 1976 [1 May 1975] 18129/75 Heading G4A Each of a plurality of processing modules PM is connected to all storage modules SM of a common memory, and each storage module returns an address parity indication to an accessing processing module, the parity indication being inverted in response to a next succeeding write operation following a read-andhold operation. The arrangement allows a processing module to lock on to a particular storage module when it is required to read data from a particular location and subsequently to write at the same location. A store access demand accepted by the access module ACC of a storage module sets a toggle RAH to inhibit a parity inverter IPAR2 during the read operation of a read-and-hold command so that the true parity bit produced by an address parity generator PAR2 is returned to the processing module for comparison with the output from a local address parity generator PAR1. A subsequent write demand resets toggle RAH if not already reset by automatic time-out to cause the inverted address parity to be returned to the processing module requesting the access, this module having its parity inverter IPAR1 enabled by the write demand, and hence an equal comparison should again result. If some other processing module attempts to access a storage module in which a read-and-hold operation is in progress, inverted address parity is returned to that processing module which forces it into a recovery sequence, as would happen if the unequal comparison of address parities resulted from corruption of the address during transmission or if the read-and-hold mechanism fails. The processing modules may be microprogrammed processors of known type and may be connected to the storage modules by X and Y buses. The X bus has a set of 24 leads for addresses and write data, three control leads redundantly coded to protect against single bit errors and specifying the requested storage operation, an ODD/EVEN parity control lead and bus valid and timing leads. The Y bus has a set of 24 leads for read data, a read data parity lead, an accumulated parity lead for successive forward data and parity control leads in a single access, and valid cycle (demand accepted), peripheral register busy, peripheral status fault and timing leads. The processing modules may be connected to separate parts of a storage module access unit or a plurality of processing modules may share a common part of an access unit via a multiplexor. |
