| 摘要 |
PURPOSE:To suppress the increase of a jitter and to obtain an output timing pulse, which is synchronous to an input pulse, by providing a means to input an input pulse to a phase comparator for every two input pulses. CONSTITUTION:A reading data control circuit 40 is provided in the front step of a phase comparator 10. Considering that a reading data signal DTIN accompanies phase lead and phase lag alternatively, this circuit 40 inputs data DTIN to the comparator 10 for every two sets of the data. Thus, the comparator 10, a low-pass filter 20 and a voltage controlled oscillator 30 process the signal DTIN, which accompanies only the phase lead or phase lag, without malfunction and an output signal VCOOUT to be synchronous to the signal DTIN can be obtained. Accordingly, the increase of the jitter in a phase synchronizing circuit can be suppressed and phase correction can be executed without fail. |
