| 摘要 |
A fail-safe "OR" logic gate circuit which includes at least a first and a second level detector each of which has a voltage breakdown device and an oscillating circuit, a resonant tank circuit connected in common with each of the oscillating circuits, an amplifying circuit coupled to each oscillating circuit, and a regulating-rectifying circuit coupled to the amplifying circuit and producing a d.c. output signal when a d.c. input signal causes either or both of the voltage breakdown devices to breakdown and to exhibit a low impedance for causing the oscillating circuits to oscillate and supply a.c. signals to the amplifying circuit for rectification by the regulating-rectifying circuit.
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